Semiconductor device and method of fabricating the same

ABSTRACT

The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. nonprovisional application claims priority under 35 U.S.C §119 to Korean Patent Application Nos. 10-2020-0037771 filed on Mar. 27,2020 and 10-2020-0095459 filed on Jul. 30, 2020 the Korean IntellectualProperty Office, the disclosures of each of which are herebyincorporated by reference in their entirety.

BACKGROUND

Some example embodiments relate to a semiconductor device and/or amethod of fabricating the same.

Semiconductor devices are beneficial in the electronic industry becauseof their small size, multi-functionality, and/or low fabrication cost.Semiconductor devices may encompass semiconductor memory devices storinglogic data, semiconductor logic devices processing operations of logicdata, and/or hybrid semiconductor devices having both memory and logicelements. Semiconductor devices have been increasingly required for highintegration with the advanced development of the electronic industry.For example, semiconductor devices have been increasingly requested forhigh reliability, high speed, and/or multi-functionality. Semiconductordevices are gradually complicated and are integrated to meet theserequested characteristics.

SUMMARY

Some example embodiments of inventive concepts provide a semiconductordevice whose electrical characteristics are improved.

Some example embodiments of inventive concepts provide a method offabricating a semiconductor device whose electrical characteristics areimproved.

According to some example embodiments a method of fabricating asemiconductor device may comprise forming a first dielectric layer on asubstrate, forming a via in the first dielectric layer, sequentiallyforming a first metal pattern, a first metal oxide pattern, a secondmetal pattern, and an antireflective pattern on the first dielectriclayer, and performing an annealing process to react the first metaloxide pattern and the second metal pattern with each other to form asecond metal oxide pattern. The forming the second metal oxide patternincludes forming the second metal oxide pattern by a reaction between ametal element of the second metal pattern and an oxygen element of thefirst metal oxide pattern.

According to some example embodiments, a semiconductor device maycomprise a substrate, a first metal pattern on the substrate, a secondmetal pattern on the first metal pattern, a via between the first metalpattern and the second metal pattern, a metal oxide pattern on thesecond metal pattern, and an antireflective pattern on the metal oxidepattern. The second metal pattern includes aluminum (Al), the metaloxide pattern includes titanium oxide, the antireflective patternincludes titanium nitride, the via includes a metallic materialdifferent from a metallic material of the second metal pattern, and thefirst metal pattern includes a metallic material different from themetallic material of the second metal pattern and the metallic materialof the via.

According to some example embodiments, a semiconductor device maycomprise a substrate, a first dielectric layer on the substrate, a metalpattern on the first dielectric layer, a metal oxide pattern on themetal pattern, an antireflective pattern on the metal oxide pattern, asecond dielectric layer on the first dielectric layer, the seconddielectric layer covering the metal pattern, the metal oxide pattern,and the antireflective pattern, a first via that penetrates the firstdielectric layer and is connected to the metal pattern, and a second viathat penetrates a portion of the second dielectric layer and isconnected to the metal pattern. The metal pattern includes aluminum(Al), the metal oxide pattern includes titanium oxide, theantireflective pattern includes titanium nitride, and the first via andthe second via include a material different from a material of the metalpattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a simplified cross-sectional view showing asemiconductor device according to some example embodiments of inventiveconcepts.

FIG. 2 illustrates a simplified cross-sectional view showing asemiconductor device according to some example embodiments of inventiveconcepts.

FIGS. 3 to 12 illustrate cross-sectional views showing a method offabricating a semiconductor device according to some example embodimentsof inventive concepts.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Some example embodiments of inventive concepts will now be described indetail with reference to the accompanying drawings to aid in clearlyexplaining the present inventive concepts.

FIG. 1 illustrates a simplified cross-sectional view showing asemiconductor device according to some example embodiments of inventiveconcepts.

Referring to FIG. 1, a semiconductor device according to some exampleembodiments of inventive concepts may include a substrate 100, a lowerdielectric layer 201, a first dielectric layer 301, a first metalpattern 310, a second dielectric layer 501, a first via 520, a thirddielectric layer 502, a second metal pattern 551, a metal oxide pattern590, an antireflective pattern 571, a second via 620, a firstpassivation layer 503, an upper dielectric layer 601, and a secondpassivation layer 603.

The substrate 100 may be or include a semiconductor substrate, such as asilicon substrate, a germanium substrate, a silicon-germanium substrate,and/or a silicon-on-insulator (SOI) substrate. A transistor 200 may beformed on or on and within the substrate 100. The transistor 200 mayinclude a gate dielectric pattern 210, a gate electrode 220, and a gatecapping pattern 230 that are sequentially stacked. The transistor 200may further include a gate spacer 240 on opposite sidewalls of each ofthe gate dielectric pattern 210, the gate electrode 220, and the gatecapping pattern 230. The transistor 200 may be provided on its oppositesides with impurity regions 100 a and 100 b serving as source/drainregions. The transistor 200 may be formed in plural on the substrate100. The transistor 200 may be an N-type transistor, or P-typetransistor.

The gate dielectric pattern 210 may include at least one of oxide,nitride, oxynitride, or metal silicate. The gate electrode 220 mayinclude a conductive material, such as tungsten (W), molybdenum (Mo),tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), and/ortantalum nitride (TaN). The gate capping pattern 230 may include siliconoxide and/or silicon nitride. The gate spacer 240 may include siliconoxide and/or silicon nitride.

The substrate 100 may be provided thereon with the lower dielectriclayer 201 that covers the transistor 200. The substrate 100 may beprovided thereon with a lower contact 250 that penetrates the lowerdielectric layer 201 and is connected to the substrate 100. The lowerdielectric layer 201 may include silicon oxide, for example, at leastone of tetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), andundoped silicate glass (USG). The lower contact 250 may include aconductive material, such as copper (Cu).

A plurality of first metal patterns 310 may be disposed on the lowerdielectric layer 201. A lowermost one of the first metal patterns 310may be connected to the lower contact 250. The first metal patterns 310may be disposed spaced apart from each other in a directionperpendicular to a top surface of the substrate 100. A plurality ofupper contacts 320 may be disposed alternately with the first metalpatterns 310. The first metal patterns 310 may be electrically connectedto each other through the upper contacts 320. The first metal patterns310 and the upper contacts 320 may include a conductive material, suchas copper (Cu). A number of layers of first metal patterns 310 may be aninteger such as one, two, three, four, five, six, seven, eight, nine,ten, or more than ten. Further a number of layers of upper contacts 320may be an integer such as one, two, three, four, five, six, seven,eight, nine, ten, or more than ten. A number of layers of the uppercontacts 320 may be one less than a number of layers of first metalpatterns 310; however, example embodiments are not limited thereto. Thefirst metal patterns 310 and the upper contacts 320 may be formed with avia-first process or a via-last process; however, example embodimentsare not limited thereto.

The lower dielectric layer 201 may be provided thereon with the firstdielectric layer 301 that covers the first metal patterns 310 and theupper contacts 320. The first dielectric layer 301 may include siliconoxide as inter-metal dielectric (IMD), for example, at least one oftetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), and undopedsilicate glass (USG).

The second dielectric layer 501 may be disposed on and may cover thefirst dielectric layer 301 and an uppermost one of the first metalpatterns 310. The second dielectric layer 501 may include silicon oxideas inter-metal dielectric (IMD), for example, at least one oftetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), and undopedsilicate glass (USG).

The uppermost first metal pattern 310 may be provided thereon with aplurality of first vias 520 that penetrate the second dielectric layer501 and are electrically connected to the uppermost first metal pattern310. A first barrier layer 510 may be disposed to intervene between thesecond dielectric layer 501 and a lateral surface of the first via 520and to extend between the uppermost first metal pattern 310 and a bottomsurface of the first via 520. The first barrier layer 510 may be formedto have a uniform thickness. The first via 520 may include a differentmaterial from that of the first metal patterns 310. For example, allmaterials, or at least one material, included in the first via 520 maybe different from any of the materials included in the first metalpatterns 310. The first via 520 may include a conductive material, suchas tungsten (W). The first barrier layer 510 may include a conductivematerial or conductive metal nitride. For example, the first barrierlayer 510 may include tungsten nitride (WN) or tungsten carbonitride(WCN).

A plurality of second metal patterns 551 may be disposed on the seconddielectric layer 501. The second metal patterns 551 may be electricallyconnected to the first vias 520. The second metal pattern 551 mayinclude a different material from that of the first metal patterns 310.For example, all materials, or at least one material, included in thesecond metal pattern 551 may be different from any of the materialsincluded in the first metal pattern 310. The second metal pattern 551may include a different material from that of the first via 520. Thesecond metal pattern 551 may include a conductive material, such asaluminum (Al). The metal oxide pattern 590 and the antireflectivepattern 571 may be sequentially formed on the second metal pattern 551.The metal oxide pattern 590 may include conductive metal oxide, such astitanium oxide (TiO2). The antireflective pattern 571 may include thesame metal element as that of the metal oxide pattern 590. Theantireflective pattern 571 may include a different material from that ofthe first barrier layer 510. For example, all materials, or at least onematerial, included in the antireflective pattern 571 may be differentfrom any of the materials included in the first barrier layer 510. Theantireflective pattern 571 may include conductive metal nitride, such astitanium nitride (TiN). The metal oxide pattern 590 may be in contactwith/direct contact with a top surface of the second metal pattern 551,and the antireflective pattern 571 may be in contact with/direct contactwith a top surface of the metal oxide pattern 590. As the metal oxidepattern 590 is formed on the second metal pattern 551, nitrogen (N) maybe prevented, or reduced in likelihood, from diffusing into the secondmetal pattern 551, and thus the second metal pattern 551 may have no orminimum or reduced concentration of nitrogen (N). The presence of themetal oxide pattern 590 may reduce resistance of semiconductor devicesand may reduce, e.g., minimize thermal stress generated from anannealing process. Alternatively or additionally, the metal oxidepattern 590 may promote diffusion of hydrogen into a semiconductorsubstrate, and thus transistors may reduce their leakage current and inparticular volatile and/or non-volatile semiconductor devices mayimprove in refresh characteristics, with the result that thesemiconductor device may be provided with improved electricalcharacteristics.

The third dielectric layer 502 may be disposed on the second dielectriclayer 501. The third dielectric layer 502 may cover a lateral surface ofthe second metal pattern 551, a lateral surface of the metal oxidepattern 590, and lateral and top surfaces of the antireflective pattern571. The third dielectric layer 502 may include silicon oxide asinter-metal dielectric (IMD), for example, at least one oftetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), and undopedsilicate glass (USG).

The first passivation layer 503 may be disposed on the third dielectriclayer 502. The first passivation layer 503 may cover the thirddielectric layer 502. The first passivation layer 503 may be formed tohave a uniform thickness on the third dielectric layer 502. The firstpassivation layer 503 may include a different material from that of thesecond dielectric layer 501 and that of the third dielectric layer 502.For example, there may not be a common material among any of the firstpassivation layer 503, the second dielectric layer 501, or the thirddielectric layer 502. The first passivation layer 503 may include one ormore of silicon nitride, silicon carbonitride, silicon oxynitride, andsilicon oxycarbonitride. The first passivation layer 503 may include,for example, one or more of SiN, SiCN, SiON, and SiOCN.

An upper pad 650 may be disposed on the first passivation layer 503. Aprotective layer 655 may be disposed on the upper pad 650. The upper pad650 may include a conductive material, such as at least one of aluminum(Al), copper (Cu), tungsten (W), or nickel (Ni). The protective layer655 may include a conductive material, conductive nitride, conductivecarbide, and/or conductive carbonitride. For example, the protectivelayer 655 may include one or more of Ti, Ta, TaN, TiN, TiSiN, W, WN, WC,and WCN.

The upper dielectric layer 601 may be disposed on the first passivationlayer 503. The upper dielectric layer 601 may cover the upper pad 650and the protective layer 655. The second passivation layer 603 may bedisposed on the upper dielectric layer 601. The second passivation layer603 may cover the upper dielectric layer 601. The second passivationlayer 603 may be formed to have a uniform thickness on the upperdielectric layer 601. The upper dielectric layer 601 may include siliconoxide as inter-metal dielectric (IMD), for example, at least one oftetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), and undopedsilicate glass (USG). The second passivation layer 603 may include oneor more of silicon nitride, silicon carbonitride, silicon oxynitride,and silicon oxycarbonitride. For example, the second passivation layer603 may include one or more of SiN, SiCN, SiON, and SiOCN.

Some of a plurality of antireflective patterns 571 may be providedthereon with a plurality of second vias 620 that penetrate a portion ofthe third dielectric layer 502, the first passivation layer 503, and aportion of the upper dielectric layer 601. The second via 620 mayelectrically connect the upper pad 650 to the second metal pattern 551.A second barrier layer 610 may be disposed to intervene between alateral surface of the second via 620, the portion of the thirddielectric layer 502, the first passivation layer 503, and the portionof the upper dielectric layer 601, while extending between theantireflective pattern 571 and a bottom surface of the second via 620.The second via 620 may include a different material from that of thesecond metal pattern 551. There may not be a common material between thesecond via 620 and the second metal pattern 551. The second via 620 mayinclude a conductive material, such as tungsten (W).

The second barrier layer 610 may include a different material from thatof the first barrier layer 510. For example, the second barrier layer610 may not include any material included in that of the first barrierlayer 510. The second barrier layer 610 may include the same material asthat of the antireflective pattern 571. For example, the second barrierlayer 610 may be the same material as that of the antireflective pattern571. The second barrier layer 610 may include a conductive material orconductive metal nitride. For example, the second barrier layer 610 mayinclude titanium nitride (TiN).

The upper pad 650, the protective layer 655, the upper dielectric layer601, and the second passivation layer 603 may be partially removed toform a first recession 605 to which a portion of the upper pad 650 isexposed.

According to some example embodiments inventive concepts, differentlyfrom that shown in FIG. 1, the upper pad 650 may not be included. Forexample, a redistribution line may be disposed instead.

FIG. 2 illustrates a simplified cross-sectional view showing asemiconductor device according to some example embodiments of inventiveconcepts. For brevity of description, differences from the semiconductordevice discussed with reference to FIG. 1 will be mainly explainedbelow.

Referring to FIG. 2, an intermediate dielectric layer 401 may beinterposed between the first dielectric layer 301 and the seconddielectric layer 501. The uppermost first metal pattern 310 may beprovided thereon with a plurality of intermediate vias 420 thatpenetrate the intermediate dielectric layer 401. The intermediate vias420 may be electrically connected to the first metal patterns 310. Anintermediate barrier layer 410 may be disposed to intervene between theintermediate dielectric layer 401 and a lateral surface of theintermediate via 420 and to extend between the uppermost first metalpattern 310 and a bottom surface of the intermediate via 420. Theintermediate barrier layer 410 may be formed to have a uniform thicknessin the intermediate dielectric layer 401. The intermediate via 420 mayinclude a conductive material, such as tungsten (W). The intermediatebarrier layer 410 may include a conductive material and/or conductivemetal nitride. For example, the intermediate barrier layer 410 mayinclude tungsten nitride (WN) and/or tungsten carbonitride (WCN).

A lower metal pattern 451 may be disposed on the intermediate dielectriclayer 401. The lower metal pattern 451 may be disposed between theintermediate via 420 and the first via 520. The lower metal pattern 451may be electrically connected to the intermediate via 420 and the firstvia 520. The lower metal pattern 451 may include a conductive material,such as aluminum (Al). A lower metal oxide pattern 490 and a lowerantireflective pattern 471 may be sequentially formed on the lower metalpattern 451. The lower metal oxide pattern 490 may include conductivemetal oxide, such as titanium oxide (TiO2). The lower antireflectivepattern 471 may include at least one of the same metal element as thatof the lower metal oxide pattern 490. The lower antireflective pattern471 may include conductive metal nitride, such as titanium nitride(TiN). The lower metal oxide pattern 490 may be in contact/directcontact with a top surface of the lower metal pattern 451, and the lowerantireflective pattern 471 may be in contact/direct contact with a topsurface of the lower metal oxide pattern 490.

As the lower metal oxide pattern 490 is formed on the lower metalpattern 451, nitrogen (N) may be prevented, or reduced in likelihood,from diffusing into the lower metal pattern 451, and thus the lowermetal pattern 451 may have no or minimum or reduced concentration ofnitrogen (N). The presence of the lower metal oxide pattern 490 mayreduce resistance of semiconductor devices and may reduce or minimizethermal stress generated from an annealing process. Alternatively oradditionally, the lower metal oxide pattern 490 may promote diffusion ofhydrogen into a semiconductor substrate, and thus transistors may reducetheir leakage current and in particular volatile and/or non-volatilesemiconductor devices may improve in refresh characteristics, with theresult that semiconductor devices may be provided with improvedelectrical characteristics.

The second dielectric layer 501 may cover a lateral surface of the lowermetal pattern 451, a lateral surface of the lower metal oxide pattern490, a lateral surface of the lower antireflective pattern 471, and aportion of a top surface of the lower antireflective pattern 471.

A semiconductor device according some example embodiments may besubstantially the same as the semiconductor device discussed withreference to FIG. 1, except that they may further include other elementsin addition to or alternative to the intermediate dielectric layer 401,the intermediate via 420, the intermediate barrier layer 410, the lowermetal pattern 451, the lower metal oxide pattern 490, and the lowerantireflective pattern 471.

FIGS. 3 to 12 illustrate cross-sectional views showing a method offabricating a semiconductor device according to some example embodimentsof inventive concepts. The semiconductor device of FIG. 1 will bepartially illustrated in the interest of brevity.

Referring to FIG. 1, a transistor 200 may be formed on a substrate 100.A lower dielectric layer 201 may be formed on the substrate 100,covering the transistor 200. On the substrate 100, a lower contact 250may be formed to penetrate the lower dielectric layer 201 and to have aconnection with the substrate 100. On the lower dielectric layer 201, aplurality of first metal patterns 310 may be formed to have connectionswith the lower contacts 250. A plurality of upper contacts 320 may beformed between and connected to the first metal patterns 310. A firstdielectric layer 301 may be formed on the lower dielectric layer 201,covering the first metal patterns 310 and the upper contacts 320.

Referring to FIGS. 1 and 3, a second dielectric layer 501 may be formedon the first dielectric layer 301, and a first barrier layer 510 and afirst via 520 may be formed in the second dielectric layer 501. Theformation of the first barrier layer 510 and the first via 520 mayinclude partially removing the second dielectric layer 501 to form a viahole that penetrates the second dielectric layer 501, and locallyforming the first barrier layer 510 and the first via 520 in the viahole. The via hole that penetrates the second dielectric layer 501 maybe formed by at least one of dry etching, wet etching, laser drilling,or mechanical drilling. The first barrier layer 510 may be formed tofill a portion of the via hole and to have a uniform thickness in thevia hole. The first barrier layer 510 may be formed by at least one of aphysical vapor deposition (PVD), chemical vapor deposition (CVD), oratomic layer deposition (ALD) process. The first via 520 may be formedto fill a remaining portion of the via hole. The first via 520 may beformed by at least one of a physical vapor deposition (PVD), chemicalvapor deposition (CVD), or atomic layer deposition (ALD) process.

A second metal layer 550 may be formed on the second dielectric layer501. The second metal layer 550 may include a conductive material, suchas aluminum (Al). The second metal layer 550 may be formed by at leastone of a physical vapor deposition (PVD), chemical vapor deposition(CVD), or atomic layer deposition (ALD) process.

Referring to FIG. 4, a second metal oxide layer 555 may be formed on thesecond metal layer 550. The second metal oxide layer 555 may be formedto have a uniform thickness. The second metal oxide layer 555 mayinclude conductive metal oxide, for example, aluminum oxide (AlOx). Thesecond metal oxide layer 555 may be formed by at least one of a physicalvapor deposition (PVD), chemical vapor deposition (CVD), or atomic layerdeposition (ALD) process.

Referring to FIG. 5, a third metal layer 560 may be formed on the secondmetal oxide layer 555. The third metal layer 560 may be formed to have auniform thickness. The third metal layer 560 may include a conductivematerial, such as titanium (Ti). The third metal layer 560 may be formedby at least one of physical vapor deposition (PVD), chemical vapordeposition (CVD), or atomic layer deposition (ALD).

Referring to FIG. 6, an antireflective layer 570 may be formed on thethird metal layer 560. The antireflective layer 570 may be formed tohave a uniform thickness. The antireflective layer 570 may include thesame metal element as that of the third metal layer 560. Theantireflective layer 570 may include conductive metal nitride, such astitanium nitride (TiN). The antireflective layer 570 may be formed by atleast one of a physical vapor deposition (PVD), chemical vapordeposition (CVD), or atomic layer deposition (ALD) process.

Referring to FIGS. 7 and 8, a photoresist layer 580 may be formed on theantireflective layer 570. The photoresist layer 580 may be irradiatedwith light 582, such as ultraviolet light, to perform exposure anddevelopment processes, and may then be formed into a photoresist pattern583 to define a region where a pattern will be formed. The photoresistpattern 583 may be used as an etching mask to pattern the second metallayer 550, the second metal oxide layer 555, the third metal layer 560,and the antireflective layer 570. When the light 582 is irradiated, theantireflective layer 570 may protect the second metal layer 550, and/ormay help to avoid standing waves within the photoresist layer 580.

Referring to FIG. 9, an etching process, such as a dry etching processand/or a wet etching process, may be performed in which the second metallayer 550, the second metal oxide layer 555, the third metal layer 560,and the antireflective layer 570 are etched to form a second metalpattern 551, a second metal oxide pattern 556, a third metal pattern561, and an antireflective pattern 571. After the etching process, thephotoresist pattern 583 may be removed by an ashing and/or stripprocess. The antireflective pattern 571 may include the same metalelement as that of the third metal pattern 561. The second metal pattern551 may include a different material, e.g. a different metal, from thatof the third metal pattern 561. The first via 520 may include adifferent material from that of the second metal pattern 551 and that ofthe third metal pattern 561.

Referring to FIG. 10, a third dielectric layer 502 may be formed on thesecond dielectric layer 501. The third dielectric layer 502 may cover alateral surface of the second metal pattern 551, a lateral surface ofthe second metal oxide pattern 556, a lateral surface of the third metalpattern 561, and lateral and top surfaces of the antireflective pattern571. A first passivation layer 503 may be formed on the third dielectriclayer 502. The first passivation layer 503 may be formed to have auniform thickness. The third dielectric layer 502 and the firstpassivation layer 503 may be formed by at least one of a physical vapordeposition (PVD), chemical vapor deposition (CVD), or atomic layerdeposition (ALD) process.

Referring to FIG. 11, an annealing process may be performed in which thesecond metal oxide pattern 556 and the third metal pattern 561 arereacted with each other to form a metal oxide pattern 590. For example,a metal element (e.g., Ti) of the third metal pattern 561 and an oxygenelement of the second metal oxide pattern 556 may react with each otherto form the metal oxide pattern 590. The metal oxide pattern 590 mayinclude conductive metal oxide, such as titanium oxide (TiO2). Theannealing process may be executed at about 300° C. to about 500° C. andmay be performed with a rapid-thermal annealing (RTA) process and/orwith a furnace process; however, example embodiments are not limitedthereto.

As the metal oxide pattern 590 is formed by the annealing process,nitrogen (N) may be prevented or reduced in likelihood from diffusinginto the second metal pattern 551, and thus the second metal pattern 551may have no or minimum or reduced concentration of nitrogen (N).Accordingly, it may be possible to reduce resistance of semiconductordevices and to reduce or minimize thermal stress generated from theannealing process. Alternatively or additionally, the metal oxidepattern 590 may promote diffusion of hydrogen into a semiconductorsubstrate, and thus transistors may reduce their leakage current and inparticular volatile and non-volatile semiconductor devices may improvein refresh characteristics, with the result that semiconductor devicesmay be provided with improved electrical characteristics.

Referring to FIG. 12, the first passivation layer 503, the thirddielectric layer 502, and the antireflective pattern 571 may bepartially removed to form a second recession 505 that exposes a portionof the antireflective pattern 571.

The method of fabricating a semiconductor device according to someexample embodiments of the present inventive concepts may besubstantially the same as that discussed with reference to FIG. 1.

A semiconductor device according to some example embodiments ofinventive concepts may include a metal oxide layer formed by annealing ametal layer and a metal nitride layer that are sequentially stacked onan aluminum line. Accordingly, it may be possible to reduce resistanceof the semiconductor device and to reduce or minimize thermal stressgenerated from the annealing process. Alternatively or additionally, themetal oxide layer may promote diffusion of hydrogen into a semiconductorsubstrate, and thus transistors may reduce their leakage current and inparticular volatile and non-volatile semiconductor devices may improvein refresh characteristics, with the result that the semiconductordevice may be provided with improved electrical characteristics.

Although inventive concepts have been described in connection with thesome example embodiments illustrated in the accompanying drawings, itwill be understood by one of ordinary skill in the art that variationsin form and detail may be made therein without departing from the spiritand essential feature of the present inventive concepts. The abovedisclosed example embodiments should thus be considered illustrative andnot restrictive.

What is claimed is:
 1. A method of fabricating a semiconductor device,the method comprising: forming a first dielectric layer on a substrate;forming a via in the first dielectric layer; sequentially forming afirst metal pattern, a first metal oxide pattern, a second metalpattern, and an antireflective pattern on the first dielectric layer;and performing an annealing process to react the first metal oxidepattern and the second metal pattern with each other to form a secondmetal oxide pattern, wherein the forming the second metal oxide patternincludes forming the second metal oxide pattern by a reaction between ametal element of the second metal pattern and an oxygen element of thefirst metal oxide pattern.
 2. The method of claim 1, whereinsequentially forming the first metal pattern, the first metal oxidepattern, the second metal pattern, and the antireflective pattern on thefirst dielectric layer includes: forming a first metal layer on thefirst dielectric layer; forming a first metal oxide layer on the firstmetal layer; sequentially forming a second metal layer and anantireflective layer on the first metal oxide layer; and etching thefirst metal layer, the first metal oxide layer, the second metal layer,and the antireflective layer.
 3. The method of claim 1, wherein the viaincludes a material different from a material of the first metalpattern, a material of the second metal pattern, or a material of thefirst metal pattern and of the second metal pattern.
 4. The method ofclaim 1, wherein the first metal pattern and the second metal patterninclude different materials from each other.
 5. The method of claim 1,wherein the first metal pattern includes aluminum (Al), and the secondmetal pattern includes titanium (Ti).
 6. The method of claim 1, whereinthe antireflective pattern includes conductive metal nitride, and theantireflective pattern includes a metal element the same as a metalelement of the second metal pattern.
 7. The method of claim 1, furthercomprising: before performing the annealing process, forming on theantireflective pattern a second dielectric layer that covers a lateralsurface of the first metal pattern, a lateral surface of the first metaloxide pattern, a lateral surface of the second metal pattern, and alateral surface of the antireflective pattern; and forming a passivationlayer on the second dielectric layer, the passivation layer covering thesecond dielectric layer, wherein the passivation layer includes amaterial different from a material of the first dielectric layer and amaterial of the second dielectric layer.
 8. The method of claim 1,wherein forming the via in the first dielectric layer includes: removinga portion of the first dielectric layer to form a via hole; forming abarrier layer that fills a portion of the via hole; and forming the viathat fills a remaining portion of the via hole.
 9. The method of claim8, wherein the barrier layer includes a material different from amaterial of the antireflective pattern.
 10. The method of claim 1,wherein the annealing process is performed at about 300° C. to about500° C.
 11. A semiconductor device, comprising: a substrate; a firstmetal pattern on the substrate; a second metal pattern on the firstmetal pattern; a via between the first metal pattern and the secondmetal pattern; a metal oxide pattern on the second metal pattern; and anantireflective pattern on the metal oxide pattern, wherein the secondmetal pattern includes aluminum (Al), the metal oxide pattern includestitanium oxide, the antireflective pattern includes titanium nitride,the via includes a metallic material different from a metallic materialof the second metal pattern, and the first metal pattern includes ametallic material different from the metallic material of the secondmetal pattern and the metallic material of the via.
 12. Thesemiconductor device of claim 11, wherein the via includes tungsten (W),and the first metal pattern includes copper (Cu).
 13. The semiconductordevice of claim 11, further comprising: a first dielectric layer and asecond dielectric layer that are sequentially arranged on the substrate;a third dielectric layer on the second dielectric layer, the thirddielectric layer covering the second metal pattern, the metal oxidepattern, and the antireflective pattern; and a passivation layer on thethird dielectric layer, wherein the first dielectric layer covers thefirst metal pattern, and the via penetrates the second dielectric layer.14. The semiconductor device of claim 13, further comprising: a barrierlayer between the second dielectric layer and a lateral surface of thevia, the barrier layer extending between the first metal pattern and abottom surface of the via, wherein the barrier layer includes metalnitride, and the barrier layer includes a material different from amaterial of the antireflective pattern.
 15. The semiconductor device ofclaim 11, further comprising: a lower dielectric layer between the firstdielectric layer and the second dielectric layer; a lower metal patternon the lower dielectric layer; and a lower via that penetrates the lowerdielectric layer and is connected to the first metal pattern and thelower metal pattern.
 16. The semiconductor device of claim 15, furthercomprising: a lower metal oxide pattern on the lower metal pattern; anda lower antireflective pattern on the lower metal oxide pattern.
 17. Thesemiconductor device of claim 16, wherein the lower metal oxide patternincludes a metal element the same as a metal element of the lowerantireflective pattern.
 18. A semiconductor device, comprising: asubstrate; a first dielectric layer on the substrate; a metal pattern onthe first dielectric layer; a metal oxide pattern on the metal pattern;an antireflective pattern on the metal oxide pattern; a seconddielectric layer on the first dielectric layer, the second dielectriclayer covering the metal pattern, the metal oxide pattern, and theantireflective pattern; a first via that penetrates the first dielectriclayer and is connected to the metal pattern; and a second via thatpenetrates a portion of the second dielectric layer and is connected tothe metal pattern, wherein the metal pattern includes aluminum (Al), themetal oxide pattern includes titanium oxide, the antireflective patternincludes titanium nitride, and the first via and the second via includea material different from a material of the metal pattern.
 19. Thesemiconductor device of claim 18, further comprising: a first barrierlayer between the first dielectric layer and a lateral surface of thefirst via, the first barrier layer extending between a bottom surface ofthe first via and a bottom surface of the first dielectric layer; and asecond barrier layer between the second dielectric layer and a lateralsurface of the second via, the second barrier layer extending betweenthe antireflective pattern and a bottom surface of the second via,wherein the first barrier layer and the second barrier layer includeconductive metal nitride, and the first barrier layer and the secondbarrier layer include different materials from each other.
 20. Thesemiconductor device of claim 19, wherein the antireflective pattern andthe second barrier layer include the same material as each other.